1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 2 preliminary* w3dg7268v-ad1 512mb- 64mx72 sdram unbuffered description the w3dg7268v is a 64mx72 synchronous dram module which consists of nine 64mx8 sdram com po nents in tsop ii package, and one 2k eeprom in an 8 pin tssop package for serial presence detect which are mounted on a 144 pin so-dimm mul ti lay er fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change without notice. features pc100 and pc133 compatible burst mode operation auto and self refresh capability lvttl compatible inputs and outputs serial presence detect with eeprom fully synchronous: all signals are registered on the positive edge of the system clock programmable burst lengths: 1, 2, 4, 8 or full page 3.3v 0.3v power supply 144 pin so-dimm ? package height option: ad1: 27.94 (1.10") pin configurations (front side/back side) pin names a0 C a12 address input (multiplexed) ba0-1 select bank dq0-63 data input/output cb0-7 check bit (data-in/data-out) clk0,ck1 clock input cke0 clock enable input cs0# chip select input ras# row address strobe cas# column address strobe we# write enable dqmb0-7 dqm v cc power supply (3.3v) v ss ground sda serial data i/o scl serial clock dnu do not use nc no connect pin front pin back pin front pin back pin front pin back 1v ss 2v ss 49 dq13 50 dq45 97 dq22 98 dq54 3 dq0 4 dq32 51 dq14 52 dq46 99 dq23 100 dq55 5 dq1 6 dq33 53 dq15 54 dq47 101 v cc 102 v cc 7 dq2 8 dq34 55 v ss 56 v ss 103 a6 104 a7 9 dq3 10 dq35 57 cb0 58 cb4 105 a8 106 ba0 11 v cc 12 v cc 59 cb1 60 cb5 107 v ss 108 v ss 13 dq4 14 dq36 61 clk0 62 cke0 109 a9 110 ba1 15 dq5 16 dq37 63 v cc 64 v cc 111 a10 112 a11 17 dq6 18 dq38 65 ras# 66 cas# 113 v cc 114 v cc 19 dq7 20 dq39 67 we# 68 nc 115 dqmb2 116 dqmb6 21 v ss 22 v ss 69 cs0# 70 a12 117 dqmb3 118 dqmb7 23 dqmb0 24 dqb4 71 nc 72 nc 119 v ss 120 v ss 25 dqmb1 26 dqb5 73 nc 74 clk1 121 dq24 122 dq56 27 v cc 28 v cc 75 v ss 76 v ss 123 dq25 124 dq57 29 a0 30 a3 77 cb2 78 cb6 125 dq26 126 dq58 31 a1 32 a4 79 cb3 80 cb7 127 dq27 128 dq59 33 a2 34 a5 81 v cc 82 v cc 129 v cc 130 v cc 35 v ss 36 v ss 83 dq16 84 dq48 131 dq28 132 dq60 37 dq8 38 dq40 85 dq17 86 dq49 133 dq29 134 dq61 39 dq9 40 dq41 87 dq18 88 dq50 135 dq30 136 dq62 41 dq10 42 dq42 89 dq19 90 dq51 137 dq31 138 dq63 43 dq11 44 dq43 91 vss 92 v ss 139 v ss 140 v ss 45 v cc 46 v cc 93 dq20 94 dq52 141 sda 142 scl 47 dq12 48 dq44 95 dq21 96 dq53 143 v cc 144 v cc
w3dg7268v-ad1 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 2 preliminary functional block diagram dqmb0 we# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cs0# dqm we# dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 we# dqm cs0# dq23 dq22 dq21 dq20 dq19 dq18 dq17 dq16 we# dqm cs0# we# dqm cs0# dq31 dq30 dq29 dq28 dq27 dq26 dq25 dq24 we# dqm cs0# dq62 dq63 dq61 dq60 dq59 dq58 dq57 dq56 dq47 dq51 dq55 dq54 dq53 dq52 dq49 dq50 dq48 dq43 dq45 dq46 dq44 dq41 dq42 dq40 dq39 dq37 dq38 dq35 dq36 dq33 dq34 dq32 we# we# dqm cs0# dqm cs0# d7 we# cs0# dqm we# dqm cs0# cs0# dqmb1 dqmb2 dqmb3 dqmb7 dqmb6 dqmb5 dqmb4 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 3 i/o 7 i/o 6 i/o 5 i/o 4 i/o 2 i/o 1 i/o 0 i/o 3 i/o 7 i/o 6 i/o 5 i/o 4 i/o 2 i/o 1 i/o 0 i/o 3 i/o 7 i/o 6 i/o 5 i/o 4 i/o 2 i/o 1 i/o 0 i/o 3 i/o 7 i/o 6 i/o 5 i/o 4 i/o 2 i/o 1 i/o 0 i/o 3 i/o 7 i/o 6 i/o 5 i/o 4 i/o 2 i/o 1 i/o 0 i/o 7 i/o 0 i/o 1 i/o 2 i/o 4 i/o 5 i/o 6 i/o 3 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 0 i/o 1 i/o 2 i/o 4 i/o 5 i/o 6 i/o 7 i/o 3 cb3 cb6 cb7 cb4 cb5 cb1 cb2 cb0 a0 cas# ras# cke0 cke: sdram d0-d8 cas#: sdram d0-d8 ras#: sdram d0-d8 scl sda a2 a1 serial pd a0-a12: sdram d0-d8 a0-a12 ba0-ba1 ba0-ba1: sdram d0-d8 d0-d8 d0-d8 *clock wiring clock input sdrams *clk0 *clk1 5 sdrams 4 sdrams *wire per clock loading table/wiring diagrams v ss v cc note: dq wiring may differ than described in this drawing, however dq/dqmb/cke/s relationships must be maintained as shown.
w3dg7268v-ad1 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 2 preliminary absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 9 w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol min typ max unit note supply voltage v cc 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 v ccq+0.3 v1 input low voltage v il -0.3 0.8 v 2 output high voltage v oh 2.4 v i oh = -2ma output low voltage v ol 0.4vi ol = +2ma input leakage current i li -10 10 a 3 note: 1. v ih (max)= 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min)= -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ccq input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. capacitance t a = 25c, f = 1mhz, v cc = 3.3v, v ref = 1.4v 200mv parameter symbol max unit input capacitance (a0-a12) c in1 36 pf input capacitance (ras#,cas#,we#) c in2 36 pf input capacitance (cke0) c in3 36 pf input capacitance (ck0) c in4 20 pf input capacitance (cs0#) c in5 36 pf input capacitance (dqm0-dqm7) c in6 7pf input capacitance (ba0-ba1) c in7 36 pf data input/output capacitance (dq0-dq63) c out 9pf data input/output capacitance (cb0-cb7) c out1 9pf recommended dc operating conditions voltage referenced to: v ss = 0v, 0c t a +70c
w3dg7268v-ad1 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 2 preliminary operating current characteristics v cc = 3.3v, 0c t a +70c version parameter symbol conditions 100/133 units note operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i ol = 0ma 1080 ma 1 precharge standby current in power down mode i cc2 cke v il (max), t cc = 10ns 35 ma active standby current in power-down mode i cc3 cke v il (max), t cc = 10ns 405 ma operating current (burst mode) i cc4 io = ma page burst 4 banks activated t ccd = 2ck 1125 ma 1 refresh current i cc5 t rc t rc (min) 2205 ma 2 self refresh current i cc6 cke 0.2v 54 ma notes: 1. measured with outputs open. 2. refresh period is 64ms.
w3dg7268v-ad1 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 2 preliminary electrical characteristics and recommended ac operating conditions ac characteristics 7 75/10 parameter symbol min max min max units notes access time from clk (pos. edge) cl = 3 t ac(3) 5.4 5.4 ns 27 cl = 2 t ac(2) 5.4 6 ns address hold time t ah 0.8 0.8 ns address setup time t as 1.5 1.5 ns clk high-level width t ch 2.5 2.5 ns clk low-level width t cl 2.5 2.5 ns clock cycle time cl = 3 t ck(3) 7 7.5 ns 23 cl = 2 t ck(2) 7.5 10 ns 23 cke hold time t ckh 0.8 0.8 ns cke setup time t cks 1.5 1.5 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 0.8 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 ns data-in hold time t dh 0.8 0.8 ns data-in setup time t ds 1.5 1.5 ns data-out high-impedance time cl = 3 t hz(3) 5.4 5.4 ns 10 cl = 2 t hz(2) 5.4 6 ns 10 data-out low-impedance time t lz 11ns data-out hold time (load) t oh 2.7 2.7 ns data-out hold time (no load) t ohn 1.8 1.8 ns 28 active to precharge command t ras 37 120k 44 120k ns active to active command period t rc 60 66 ns active to read or write delay t rcd 15 20 ns refresh period (8,192 rows) t ref 64 64 ms auto refresh period t rfc 66 66 ns precharge command period t rp 15 20 ns active bank a to active bank b command t rrd 14 15 ns transition time t t 0.3 1.2 0.3 1.2 ns 7 write recovery time t wr 1 clk + 7ns 1 clk + 7ns -24 14 15 ns 14, 25 exit self refresh to active command t xsr 67 75 ns 20
w3dg7268v-ad1 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 2 preliminary ac functional characteristics parameter symbol 7 75/10 units notes read/write command to read/write command t ccd 11t ck 17 cke to clock disable or power-down entry mode t cked 11t ck 14 cke to clock enable or power-down exit setup mode t ped 11t ck 14 dqm to input data delay t dqd 00t ck 17 dqm to data mask during writes t dqm 00t ck 17 dqm to data high-impedance during reads t dqz 22t ck 17 write command to input data delay t dwd 00t ck 17 data-in to active command t dal 45t ck 15, 21 data-in to precharge command t dpl 22t ck 16, 21 last data-in to burst stop command t bdl 11t ck 17 last data-in to new read/write command t cdl 11t ck 17 last data-in to precharge command t rdl 22t ck 16, 21 load mode register command to active or refresh command t mrd 22t ck 26 data-out to high-impedance from precharge command cl = 3 t roh(3) 33t ck 17 cl = 2 t roh(2) 22t ck 17
w3dg7268v-ad1 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 2 preliminary notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v cc , v ccq = +3.3v; = 25c; pin under test biased at 1.4v. f = 1 mhz, ta 3. i dd is dependent on output loading and cycle rates.speci? ed values are obtained with mini-mum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum speci? cations are used only to indicate cycle time at which proper operation over the full temperature range (0c 70c) is t a ensured. 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v cc and v ccq must be powered up simultaneously. v ss and v ssq must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate speci? cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a mono-tonic manner. 9. outputs measured at 1.5v with equivalent load: q 50pf 10. t hz de? nes the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v ih (min) and no longer at the 1.5v crossover point. 12. other input signals are allowed to transition no more than once every two clocks and are other-wise at valid vih or vil levels. 13. i dd speci? cations are tested after the device is properly initialized. 14. timing actually speci? ed by t cks ; clock(s) speci? ed as a reference only at minimum cycle rate. 15. timing actually speci? ed by t wr plus t rp ; clock(s) speci? ed as a reference only at minimum cycle rate. 16. timing actually speci? ed by t wr . 17. required clocks are speci? ed by jedec functionality and are not dependent on any timing parameter. 18. the i dd current will increase or decrease in a proportional amount by the amount the frequency is altered for the test condition. 19. address transitions average one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 7.5ns for 75/10 and 7. 22. v ih overshoot: v ih (max) = v ccq + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il under-shoot: v il (min) = -2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is de? ned as a signal cycling within timing constraints speci? ed for the clock pin) during access or precharge states (read, write, including t wr , and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget (t rp ) begins 7.5ns/7ns after the ? rst clock delay, after the last write is executed. 25. precharge mode only. 26. jedec and pc100, pc133 specify three clocks. 27. t ac for 75/10/7 at cl = 3 with no load is 4.6ns and is guaranteed by design. 28. parameter guaranteed by design. 29. for 75/10, cl = 3, t ck = 7.5ns; for 7, cl = 2, t ck = 7.5ns 30. cke is high during refresh command period t rfc (min) else cke is low. the i dd6 limit is actually a nominal value and does not result in a fail value.
w3dg7268v-ad1 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 2 preliminary note: for industrial temperature range product, add an "i" to the end of the part number. ordering information speed cas latency height* W3DG7268V10AD1 100mhz cl=2 27.94 (1.10) max w3dg7268v7ad1 133mhz cl=2 27.94 (1.10) max w3dg7268v75ad1 133mhz cl=3 27.94 (1.10) max package dimensions for ad1 3.99 (0.157) 2.01 (0.079 min) 67.72 (2.661 max) 32.79 (1.291) 4.60 (0.181) 1.50 (0.059) 28.2 (1.112) 23.14 (0.913) 19.99 (0.787) 27.94 (1.10) max 3.81 (0.150) max. 0.99 (0.039) ( 0.004) wedc 300 package dimensions for ad1 * all dimensions are in millimeters and (inches).
w3dg7268v-ad1 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs october 2004 rev. 2 preliminary document title 256mb - 64mx72 sdram unbuffered revision history rev # history release date status rev 0 created datasheet 6-2-03 advanced rev 1 1.1 updated cap and i dd spec. 1.2 added ad1 package option 1.3 created document title page 1.4 moved from advanced to preliminary 6-04 preliminary rev 2 2.1 added ac spec 2.2 updated cap spec. 10-13-04 preliminary
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